module tb_top();

reg     [31:0]  data_in         ;
reg             push            ;
reg             clk_i           ;
reg             rstn_i          ;
wire            full            ;

wire    [31:0]  data_out        ;
reg             pop             ;
reg             clk_o           ;
reg             rstn_o          ;
wire            enpty           ;


my_interface input_if  (clk_i , rstn_i);
my_interface output_if (clk_o , rstn_o);

initial begin
        uvm_config_db#(virtual my_interface)::set(null , "uvm_test_top.iagent.drv" , "vif" , input_if);
end



initial begin
        clk_i = 0 ;
        forever begin
                #100 clk_i = ~clk_i ;
        end
end

initial begin
        clk_o = 0 ;
        forever begin
                #100 clk_o = ~clk_o ;
        end
end

initial begin
        rstn_i = 1'b0 ;
        rstn_o = 1'b0 ;
#200
        rstn_i = 1'b1 ;
        rstn_o = 1'b1 ;
end




initial begin
        $fsdbDumpfile("vcs_dump.fsdb");
	$fsdbDumpvars(0,tb_top);
        run_test("my_env");
end

afifo  #( 32  ,   4)  dut 
(
   /*     input   wire                  */ .clk_i     ( clk_i   ),
   /*     input   wire                  */ .rstn_i    ( rstn_i  ),
   /*     input   wire                  */ .push      ( push    ),
   /*     input   wire  [DATA_SIZE-1:0] */ .DATA_IN   ( data_in ),
   /*     output  wire                  */ .fifo_full ( full    ),

   /*     input   wire                  */ .clk_o     ( clk_o   ),
   /*     input   wire                  */ .rstn_o    ( rstn_o  ),
   /*     input   wire                  */ .pop       ( pop     ),
   /*     output  wire  [DATA_SIZE-1]   */ .DATA_OUT  ( data_out),
   /*     output  wire                  */ .fifo_empty( empty   )
);


endmodule
